In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers.
The ongoing advances in the field of fabricating miniaturized electronic integrated circuits (ICs) has involved the fabrication of multiple layers of interconnects, or the layers of separate electrical conductors which are formed on top of a substrate and connect various functional components of the substrate and other electrical connections to the IC. Electrical connections between the interconnect layers and the functional components on the substrate are achieved by via interconnects, which are post- or plug-like vertical connections between the conductors of the interconnect layers and the substrate. ICs often have five or more interconnect layers formed on top of the substrate.
Only a relatively short time ago, it was impossible or very difficult to construct an IC with more than one or two layers of interconnects. The topology variations created by forming multiple layers on top of one another resulted in such significant depth of focus problems with lithographic processes that any further additions of layers were neardly impossible to achieve. However, recent advances in semiconductor fabrication planarization techniques, such as chemical mechanical polishing (CMP), have been successful in smoothing relatively significant variations in the height or topography of each interconnect layer. As a result of the smoothing, or planarization, conventional lithographic processes are repetitively used without significant limitation to form considerably more layers of interconnects than had previously been possible.
Because the thickness of metal films deposited on substrates is important, testing of the metal film thicknesses is regularly carried out during semiconductor fabrication. One of the methods used to test the thickness of a metal film involves the use of a Rudolph Metapulse tool, which measures laser-induced sound wave pulses in the film to obtain film thickness. The tool directs the sound wave pulses against the metal film, and the pulses travel through the film to the metal film/insulative layer interface. Some of the sound wave pulses are reflected from the interface and emitted from the surface of the metal film, where they are detected by a sound detector. The time which elapses from impingement of the sound wave pulses against the metal film, to emission of the pulses from the film to the sound detector, is translated into thickness of the metal film.
Another method which is frequently used to measure the thickness of a metal film involves the use of a laser metrology tool to direct high-energy laser beam through a metal film deposited on a test wafer. However, one of the drawbacks associated with the laser metrology tool is the lack of a calibration method to ensure accurate impingement of the laser beam against the desired target area on the metal film. Furthermore, during the course of repeated use the laser beam is susceptible to baseline drifting. Accordingly, a device and method is needed to calibrate a laser metrology tool and prevent baseline drifting of a laser beam during repeated use of the tool.
An object of the present invention is to provide a test device and method for calibrating a laser metrology tool.
Another object of the present invention is to provide a test device and method for ensuring accurate impingement of a laser beam against a target.
Still another object of the present invention is to provide a test device and method which enables corrective adjustments to be made in the alignment of a laser beam with respect to a target area on a substrate.
Yet another object of the present invention is to provide a test device which is suitable for ensuring and maintaining alignment of a laser beam with respect to a target area on a substrate, which test device includes a substrate with a calibration pattern provided thereon.
A still further object of the present invention is to provide a novel test device and laser alignment calibration method which is suitable for aligning a laser beam with respect to a target area on a film to measure the thickness or other aspects or qualities of the film.
Yet another object of the present invention is to provide a test device and laser alignment calibration method which is suitable for use in a variety of industrial technologies, particularly semiconductor fabrication technology.